1. Field of Use
This invention relates to multiplication system and apparatus, more particularly to system for multiplying numbers in binary form.
2. Prior Art
In general, it is well known to perform multiplication operations by generating required multiples of a multiplicand during a multiplication operation in contrast to prestoring multiples. An example of this certain type of apparatus is disclosed in U.S. Pat. No. 3,730,425 and assigned to the same assignee as name herein. The patented apparatus operates to multiply the multiplier by two (i.e., shifts the multiplier left one bit) before beginning the multiplication operation. Thereafter, during the multiplication operation, circuits included in the multiplication apparatus select one of a number of multiplication factors in accordance with pairs of multiplier bits. While the patented apparatus halves the number of cycles normally required for a multiplication operation, the time for performing a multiply operation is still considerable especially where the apparatus is required for use in a system which employs high speed circuits such as current mode logic circuits. Also, as discussed in the subject patent, others have suggested speeding up multiplication by examining multiplier bits in pairs, and adding different multiples to a number of series connected adders. An example of this type of multiplication is described in the text, "The Logic of Computer Arithmetic", by Ivan Flores, published by Prentice-Hall Inc., copyright 1963.
Other types of multiplication apparatus have employed prestored multiples which are generated prior to the multiplication operation, the multiples are selected in accordance with the values of multiplier digits. An example of this type of apparatus is disclosed in U.S. Pat. No. 3,641,331 assigned to the same assignee as named herein. While the patented apparatus reduces the number of multiples required to be stored and the time required for generating all of the remaining multiples, considerable time is still required for generating and storing the multiples prior to the multiplication operation.
Accordingly, it is a primary object of the present invention to provide improved multiplication system and method.
It is another object of the present invention to provide binary multiplication apparatus which minimizes the number of cycles required to perform multiplication operations in response to multiply instructions.
it is a further object of the present invention to provide high speed multiply apparatus suitable for operation with high speed integrated circuits.
It is still a further object of the present invention to provide multiply apparatus implementable with high speed integrated circuits such as current mode logic circuits.